Structure of 40 Gbit/s QSFP+ Parallel Optical Transceiver Module

Why 40G QSFP+ Parallel Optical Transceiver Is Important

With the increasing demand for bandwidth in data communication and Internet applications, the 10 Gbit/s system has gradually been unable to meet the needs of optical communication. A new generation of optical fiber and higher rate optical modules have become the focus of attention. In order to meet the market demand, many new optical network devices and optical modules are emerging. 40 Gbit/s optical modules have become the focus of intensive research and development of major optical communication suppliers because of their advantages of high speed, many channels, low power consumption, and small volume. It is undeniable that 40 Gbit/s optical modules, such as 40G QSFP+ SR4, LR4, PSM4, ER4, etc. will play an important role in high-speed and high-capacity data transmission and have huge market prospects.

As one of the implementation schemes of high-speed and high-capacity optical transmission, parallel optical transmission and reception technology fully relies on the repetition of channels to realize high-speed and high-capacity transmission, which has considerable advantages in technology and cost. This paper introduces the composition and structure design of the 40G QSFP+ optical module. The module design mainly adopts the driver chip integrating 4 channels and the detector chip integrating 4 channels, which reduces the number of devices and the design complexity of the module, so as to achieve the purpose of low cost.

Structure and Working Principle of 40G QSFP+ Transceiver

Composition and Structure of 40G QSFP+ Transceiver

The 40 Gbit/s QSFP+ optical module is mainly composed of the photoelectric chip, driving circuit chip, receiving circuit chip, MCU (microcontroller), and EEPROM (electrically erasable programmable read-only memory).

The main function of the driving circuit chip is to process the modulated electrical signal accordingly and provide the laser with a maximum 10mA modulation current and bias current to drive the laser to emit optical signals.

The main function of the receiving circuit chip is to amplify the current signal converted from the PD (Photodetector) array. The chip is composed of TIA (Transimpedance Amplifier) and LA (Limiting Amplifier), which converts the current signal into a digital voltage signal. The minimum photocurrent signal that can be processed is 20μA. The output signal is at CML (current mode logic) level. The operating voltage of the module is 3.3V.

How 40G QSFP+ Transceiver Works

The transmission signal of the 40G QSFP+ optical module enters from the four pairs of differential data input pins of the driving chip. After passing through the equalizer, differential amplifier and pre-emphasis circuit of the input part of the driving chip, the bias current, and modulation current signal are output by the driving output pin and sent to the positive pole of VCSEL (vertical cavity surface emitting laser). Finally, the electrical/optical conversion is carried out and the optical signal is output through the optical port. The laser is a bare chip without APC (automatic power control) function circuit, but bits 4 ~ 7 of the diagnostic control register (0x04) can set the bias current value of each channel, and the bias current I bias of any channel is output by the control current pin, so as to realize the purpose of monitoring the optical power emitted by the laser. The working temperature of the module can be monitored through the voltage signal output by the analog voltage pin of the thermometer and the temperature proportional current output by the control current pin.

The receiving chip provides a bias voltage for the PIN (photodiode) detector, which is connected to the N terminal of the detector. The weak electrical signal after optical/electrical conversion flows into the receiving chip from the P terminal of the detector. After the signal is amplified by TIA and LA, the high-speed data signal is output by the differential output data pin and sent to the electrical interface. The receiving strength pin is controlled by the RSSI bit in the channel configuration register and the ITHERMRSSI bit in the device register. It can output temperature signal or TIA input current of any channel

The monitoring function of the module is mainly completed by MCU. According to the 2-wire interface protocol defined by SFF-843 6 protocol, the special register can be read and written through I2C bus, so as to monitor the temperature of the photoelectric chip of the module, the bias current at the transmitting end, the modulation current, the receiving strength current at the receiving end and the loss alarm.


The 40G QSFP+ parallel optical module has excellent photoelectric performance and can be used as the best solution for high-speed computing, server cluster, Infiniband (infinite broadband technology), Ethernet switching and core router. The module adopts a high-speed integrated driver chip and receiver chip, which reduces the design complexity and the overall cost. QSFPTEK is an original brand of fiber optic transceiver factory outlet, it provides high-quality 40G QSFP+ transceivers at a very reasonable price. Welcome to consult via